1. Field of the Invention
The present invention generally relates to computer memory systems and, more particularly, to memory systems having dynamic random access memories (DRAMs) and to control methods such memory systems.
2. Discussion of Background
There are conventionally combination semiconductor memories wherein flash memory (capacity: 32 megabits) and static random access memory (SPAM (capacity: 4 megabits)) on a stack chip (stack) are integrally sealed in an FBGA (Fine pitch Ball Grid Array) package. The flash memory and the SRAM use the input/output electrodes of the FBGA package for address input terminals and data input/output terminals in common. However, the control terminals of one of them is independent of those of the other.
There are also combination semiconductor memories wherein a flash memory chip and DRAM chips are integrally sealed in a lead frame-type package. In this type of combination semiconductor memory, the flash memory and the DRAMs use the input/output electrodes of the package for address input terminals, data input/output terminals, and control terminals in common for input/output.
There are also systems consisting of flash memory which is treated as main storage, cache memory, a controller, and CPU. There are also semiconductor memories consisting of flash memory, DRAM, and a data transfer control circuit (data transfer controller). There are also memories wherein flash memory and SRAM are packaged on one and the same semiconductor chip. There are also flash I/O cards wherein flash memory and SRAM are packaged. There are also systems consisting of flash memory, cache memory, a controller, and CPU. Some of these systems are provided in more detail in the following references. “Data Sheet of Combination Memory (Stacked CSP), Flash Memory+RAM,” Model LRS1380, [online], Dec. 10, 2001, Sharp Corporation, [Retrieved on Aug. 21, 2002], Internet URL:
<http://www.sharp.co.jp/products/device/flash/cmlist.html>. JP-A No. 299616/1993 official gazette. Specification for European Patent No. 0566306 laid open. JP-A No. 146820/1995 official gazette. JP-A No. 5723/2001 official gazette. JP-A No. 357684/2001 official gazette. JP-A No. 137736/1996 official gazette. JP-A No. 510612/2001 official gazette.
The sizes of applications, data, and work areas used in cellular phones have been increased due to an increase in functions added to the cellular phones (e.g. delivering of music, game, etc.). It is expected that flash memories and SRAMs with higher capacities will be required. Further, the performance of recent cellular phones has been remarkably enhanced, and needs for large-capacity memories have grown.
Flash memories presently used in cellular phones are NOR-type flash memories using a memory array method called NOR configuration. The NOR configuration is an array configuration with the reduced parasitic resistance of memory cell array. In the NOR configuration, the resistance is reduced by providing metal bit line contacts at a rate of one contact to two memory cells connected in parallel. On this account, the read time is about 80 ns, which is substantially equal to the read time in SRAMs. However, since one contact must be provided for two cells, the proportion of the contact portion to the chip area is high and the area of one bit per memory cell is increased. This poses a problem in that needs for higher capacity cannot be achieved.
Also, typical large-capacity flash memories include AND-type flash memory which uses AND configuration for memory array, and NAND-type flash memory which uses NAND configuration. In these flash memories, one bit line contact is provided for 16 to 128 cells, and high-density memory arrays are obtained. Therefore, the area of one bit per memory cell can be made smaller than that in NOR-type flash memories, and needs for higher capacities can be achieved. On the other hand, the read time before the first data is outputted is as long as about 25 μs to 50 μs. Unfortunately, this read time would impair compatibility with SRAMs.